Phased-lock loop (PLL) synchronizes the frequency of output and input signals. The output signal is generated internally as part of the phased-lock loop; specifically from its variable-frequency oscillator (VFO).
PLLs are primary used for clock synchronization within IC packages, encompassing the whole or parts of the IC’s (signal processing) circuitry within its loop in place of the VFO (though the IC’s circuitry itself normally contains a clock source, crystal or otherwise, within it). This eliminates race conditions between the inputs and outputs of the said circuit.
PLLs are also used for demodulation; e.g., in a radio receiver for both AM and FM signals.
Finally, they are used in frequency synthesis. Frequency synthesizers create multiple frequencies based on the divider value in the feedback loop and the reference frequency (from master oscillator, normally a quartz crystal). This allows very high frequencies or very low frequencies to be generated from one crystal source.
This type of synthesizer, however, cannot operate over a very wide frequency range as the comparator will have a limited bandwidth and may suffer from aliasing problems.
A simple PLL consists of a phase detector, a loop filter and a VFO. In analog or linear PLL (see https://en.wikipedia.org/wiki/Phase-locked_loop#Variations), these basic components correspond to:
Analog multiplier as Phase detector
Passive or Active low-pass filter as Loop filter
Voltage-controlled oscillator, which falls under analog VFO category.
One implementation of analog PLL is as follow:
The specific values of these components are not easy to determine via trial and error. They are often determined via modeling and simulation. In practice, it is usually easier to just buy an off-the-shelf PLL chip than trying to construct one.